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ARM L2 Cache Verification.pdf

advanced-techniques-for-arm-l2-cache-verification-in-an-accelerated-hardware-and-software-environment.pdf
Preview of ARM L2 Cache Verification
🔗 Source: dvcon-proceedings.org
📊 Size: 416 KB
👤 Author: Galen Blake
⬇️ Downloads: 135

Summary

High-end ARM-based SOC designs implement L2 cache controllers for improved system performance and memory access management. Verifying correct operation and performance in such systems is crucial. This paper presents techniques for verifying L2 cache operation and performance in systems with concurrent software and hardware accesses. A centralized testbench manages both types of accesses, utilizing intelligent testbench techniques to systematically manage the verification state space and generate test scenarios. A hardware-accelerated simulation environment efficiently simulates a large number of scenarios, and results of the work are presented. The approach uses a graph-based method to test the complete scope of the protocol, ensuring complete coverage of the ACP-related protocol space and efficient coverage of corner cases.

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Description

High-end ARM-based SOC designs implement L2 cache controllers for improved system performance and memory access management.

Technical Information

  • File Format: PDF
  • File Size: 416 KB
  • Pages: 5
  • Language: EN
  • Author: Galen Blake
  • Total Downloads: 135
  • Last Updated: 3 hours ago

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