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1093-Poster-A-HW-and-SW-integrated-power-optimization-approaches-with-power-aware-simulations-at-SOC.pdf

🔗 Source: dvcon-proceedings.org

📊 Size: 1.39 MB

👤 Author: Laura Leblanc

⬇️ Downloads: 34

Summary

A systematic approach is used to target efficient and smooth verification flow for low-power simulations for large SOCs, involving analysis of power/voltage/clock domains, defining verification scope, and using checkers to reinforce power operations isolation, level shifters, and retention. The proposed methodology includes a hardware and software integrated power optimization approach with power-aware simulations at the SOC level, using techniques such as power gating, clock gating, and voltage scaling to achieve significant power savings, with results showing up to 91% power savings in block-level power down states/scenarios.

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Description

A systematic approach is used to target efficient and smooth verification flow for low-power simulations for large SOCs, involving analysis of...

Technical Information

File Format: PDF
File Size: 1.39 MB
Pages: 1
Language: EN
Author: Laura Leblanc
Total Downloads: 34
Last Updated: 3 weeks ago

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