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asic-strength-verification-in-a-fast-moving-fpga-world-poster.pdf

🔗 Source: dvcon-proceedings.org

📊 Size: 150 KB

👤 Author: Bryan Murdock

⬇️ Downloads: 75

Summary

ASIC-strength verification in the FPGA world requires addressing short release cycles, mixed and matched features, and small teams. Success has been achieved with tools and techniques such as automation with Python, distributed version control (DVC) using Mercurial and Git, a configuration-driven build system, and web-based code reviews using Review Board. Future work includes automating register maintenance using commercial register tools to generate code and documentation from a single definitive source.

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Description

ASIC-strength verification in the FPGA world requires addressing short release cycles, mixed and matched features, and small teams.

Technical Information

File Format: PDF
File Size: 150 KB
Pages: 1
Language: EN
Author: Bryan Murdock
Total Downloads: 75
Last Updated: 2 months ago

Document Overview

This PDF document about Download provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into Download.