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exhaustive-latch-flow-through-verification-with-formal-methods.pdf

🔗 Source: dvcon-proceedings.org

📊 Size: 377 KB

👤 Author: Stephen Sunter

⬇️ Downloads: 70

Summary

Exhaustive latch flow-through verification is crucial in latch-based designs to ensure data integrity and avoid yield loss due to random scan values during manufacturing test. The proposed technique utilizes formal methods to validate latch flow-through problems by reporting all potential data racing conditions as assertions and feeding them into formal tools. The technique also employs multi-cycle-path analysis to filter out false negatives, specifically "data-blocking" cases where data feeding through the destination latch can be blocked. The proposed technique is proven to be fast and exhaustive, catching real silicon bugs timely, and has been successfully demonstrated through multiple experiments.

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Description

Exhaustive latch flow-through verification is crucial in latch-based designs to ensure data integrity and avoid yield loss due to random scan values during...

Technical Information

File Format: PDF
File Size: 377 KB
Pages: 6
Language: EN
Author: Stephen Sunter
Total Downloads: 70
Last Updated: 2 months ago

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