Ferroelectric FET-Based Circuits For Logic-in-Memory Computing: A Comprehensive Study.pdf

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Preview of Ferroelectric FET-Based Circuits for Logic-in-Memory Computing: A Comprehensive Study
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Summary

# POLITECNICO DI TORINO
## Corso di Laurea Magistrale in Ingegneria Elettronica
## Tesi di Laurea Magistrale: Ferroelectric FET–based circuits for Logic–in–Memory computing

### Relatore: Prof. Mariagrazia Graziano
### Correlatore: Prof. Giovanna Turvani
### Candidato: Danilo Franco
### Luglio 2021

Questa tesi è pubblicata sotto licenza Creative Commons.

## Indice
1. Abstract
...5

2. State of the art
...9
- 2.1 Logic–in–Memory (LiM)
- 2.1.1 Architettura di Von Neumann
- 2.1.2 LiM con tecnologia CMOS standard
- 2.2 Oltre–CMOS tecnologie
- 2.2.1 Dispositivi di memoria
- 2.2.2 Celle intelligenti e logica

3. FeFET SPICE model
...49
- 3.1 Modello fisico FeFET
- 3.1.1 Equazione di Landau-Khalatnikov
- 3.1.2 Modello Preisach
- 3.2 Calibrazione sperimentale FeFET
- 3.3 Simulazione e caratterizzazione FeFET
- 3.3.1 Schema e testbench
- 3.3.2 Impatto dello spessore del ferroelettrico
- 3.3.3 Risposta in frequenza dell'histeresi
- 3.3.4 Altre misurazioni
- 3.4 Cellula di memoria di base FeFET–based

4. FeFET–based memory array
...61
- 4.1 Topologia
- 4.1.1 Architettura NAND
- 4.1.2 Architettura NOR
- 4.2 Array di memoria NOR FeFET: schemi
- 4.2.1 Array 8x8
- 4.2.2 Array di dimensioni maggiori
- 4.3 Amplificatore di senso
- 4.4 Testbench e script per l'array di memoria NOR FeFET
- 4.4.1 Script Python
- 4.5 Misurazioni e prestazioni dell'array di memoria NOR FeFET
- 4.5.1 Ritardi
- 4.5.2 Consumo energetico

5. Programmable FeFET–based Logic in Memory
...89
- 5.1 Panoramica
- 5.2 Template LiM
- 5.2.1 Schema
- 5.2.2 Testbench
- 5.3 Circuiti LiM per il calcolo
- 5.3.1 Cellula LUT
- 5.3.2 Cellula AND–OR
- 5.3.3 Cellula a 3 funzioni
- 5.3.4 Cellula XOR
- 5.3.5 Cellula Full Adder
- 5.3.6 Cellula Majority Voter
- 5.4 Caratterizzazione Liberty per LiM
- 5.4.1 Scopi
- 5.4.2 Template file Liberty
- 5.5 Risultati
- 5.6 Conclusioni e lavori futuri

## Appendici
- FeFET model Verilog–A source code
...133
- Python scripts per la gestione dell'array
...149
- Operations script
- Signals script

## Bibliografia
...155

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  • File Format: PDF
  • File Size: 8.41 MB
  • Pages: 158
  • Language: EN
  • Total Downloads: 33
  • Last Updated: 1 day ago

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