TLBs.pdf

Paging can lead to high performance overheads due to the need for mapping information, which is typically stored in physical memory, requiring an extra memory lookup for each virtual address. To speed up address translation, a translation-lookaside buffer (TLB) is used, which is a hardware cache of popular virtual-to-physical address translations. The TLB checks for the desired translation before consulting the page table, reducing the overhead of paging. If the translation is found in the TLB (a TLB hit), the translation is performed quickly; if not (a TLB miss), the page table must be accessed, resulting in a higher cost. The goal is to minimize TLB misses, which can slow down program execution. An example of accessing an array demonstrates how a TLB can improve performance, with a TLB hit rate of 70% in this case.