AXI4-Stream To AXI4-MM Bridge.pdf

The Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE (V1.1.0) is an AXI4-Stream to AXI4 Memory Map Bridge IP Core, accepting AXI4-Stream data and control input, converting control TID to an AXI4 Memory Map address, and signaling a DMA Controller for data read via an AXI4 Slave Memory Map read channel. It works with Digital Blocks' DMA Controller for data transfers between AXI4-Stream peripherals/network interfaces and memory/other peripherals. Key features include:

- Supports 16 AXI4-Stream channels (customizable).
- Enables peripheral-to-memory, peripheral-to-peripheral, network-to-memory, and network-to-peripheral data transfers.
- Offers individual interface data widths from 8 to 1024 bits.
- Includes an interrupt controller for diagnostics.
- Provides a fully-synchronous, synthesizable Verilog RTL core.

The IP Core comes with a test suite, and Digital Blocks offers various evaluation methods. Deliverables include synthesizable RTL Verilog, technology-specific netlists, Synopsys Design Constraints, simulation test bench, datasheet, and user manual. For technical, pricing, and support information, contact Digital Blocks, Inc.