DB9200AXI4 2D Graphics Hardware Accelerator IP Core.pdf

The Digital Blocks DB9200AXI4 2D Graphics Hardware Accelerator / Engine Verilog IP Core renders graphics frames through various operations. It generates bitmaps from graphics instructions, combines existing bitmaps on and off-screen using 256 Raster Operations, and performs Alpha Blend operations of bitmaps. The DB9200 2D Graphics Hardware Engine also provides options for higher graphics performance as a Graphics Processing Unit (GPU), including Display List Processing Unit, Parallel Pixel Processing, and Memory Interface Units with DMA Controller.

The DB9200AXI4 2D Graphics Engine Verilog IP Core is embedded within an ASIC, ASSP, or FPGA component and features Bit Block Transfer, Raster Operations, and BitBLT Draw Features. It supports various graphics operations, including line draw, circle draw, and ellipse draw, as well as command FIFO or link-list display processing unit and frame buffer and display features.

The DB9200AXI4 is available in RTL Verilog, along with synthesis scripts, a simulation test bench with expected results, reference design, datasheet, and user manual. The IP Core is warranted against defects for three years, and one year of phone and email technical support is included. Additional maintenance and support options are available.