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I2C Controller.pdf

DB-I2C-MS-Hs-Mode-DS-V1_1.pdf
Preview of I2C Controller
🔗 Source: digitalblocks.com
📊 Size: 248 KB
👤 Author: Digital Blocks, Inc.
⬇️ Downloads: 231

Summary

The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core is a Master/Slave I2C controller that interfaces a microprocessor to an I2C bus, supporting Hs-Mode (3.4 Mbit/s), Fast-Mode Plus (1 Mbit/s), Fast-Mode (400 Kbit/s), and Standard-Mode (100 Kbit/s). It features a parameterized FIFO, finite state machine control, and enhanced system-level features, including CPU interface, SCL/SDA spike filtering, and repeated start capabilities. The controller is fully synchronous, synthesizable, and compliant with AMBA, Avalon, and I2C specifications. It is available in synthesizable RTL Verilog or VHDL, with deliverables including a simulation test bench, datasheet, and user manual.

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Description

The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core is a Master/Slave I2C controller that interfaces a microprocessor to an I2C bus, supporting Hs-Mode...

Technical Information

  • File Format: PDF
  • File Size: 248 KB
  • Pages: 4
  • Language: EN
  • Author: Digital Blocks, Inc.
  • Total Downloads: 231
  • Last Updated: 2 weeks ago

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This PDF document about I2C Controller provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into I2C Controller.

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