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ZBT SRAM.pdf

AS8C803601_801801.pdf
Preview of ZBT SRAM
🔗 Source: alliancememory.com
📊 Size: 2.67 MB
👤 Author: adickins
⬇️ Downloads: 48

Summary

The AS8C803601/801801 are 3.3V high-speed 9,437,184-bit synchronous SRAMs with a Zero Bus Turnaround (ZBT) feature, eliminating dead bus cycles between reads and writes. They have 256K x 36 and 512K x 18 memory configurations, supporting high-performance system speeds of up to 150MHz. The devices feature internally synchronized output buffer enable, single R/W control pin, positive clock-edge triggered address and control signal registers, 4-word burst capability, individual byte write control, and three chip enables for simple depth expansion. They operate on a 3.3V power supply and have a 3.3V I/O supply, with power-down controlled by the ZZ input. The SRAMs are packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP).

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Description

The AS8C803601/801801 are 3.3V high-speed 9,437,184-bit synchronous SRAMs with a Zero Bus Turnaround (ZBT) feature, eliminating dead bus cycles between reads...

Technical Information

  • File Format: PDF
  • File Size: 2.67 MB
  • Pages: 21
  • Language: EN
  • Author: adickins
  • Total Downloads: 48
  • Last Updated: 1 week ago

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This PDF document about ZBT SRAM provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into ZBT SRAM.

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