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LVDS Combo Cell.pdf

nSIO_TS40LP_2V5_1V1_COMBO_PB.pdf
Preview of LVDS Combo Cell
🔗 Source: nsilition.com
📊 Size: 293 KB
👤 Author: Guillaume Pollissard
⬇️ Downloads: 103

Summary

The NSIOTS40LP2V51V1COMBO is a combo cell combining an LVDS receiver, driver, or transceiver with a double CMOS GPIO, powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP technology, suitable for high-speed data communications, including point-to-point, point-to-multipoint, bus-based IC, intra-package, backplane, and high-speed serial communications, with features including standard-compliant to TIA/EIA-644-A-2001, built-in low parasitic ESD protection, and adjustable output common mode voltage, driving current, and output driving current, with a data rate of up to 2 Gbps.

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Description

The NSIO_TS40LP_2V5_1V1_COMBO is a combo cell combining an LVDS receiver, driver, or transceiver with a double CMOS GPIO, powered at 2.5V/1.1V or 1.8V/1.1V,...

Technical Information

  • File Format: PDF
  • File Size: 293 KB
  • Pages: 2
  • Language: EN
  • Author: Guillaume Pollissard
  • Total Downloads: 103
  • Last Updated: 1 month ago

Document Overview

This PDF document about LVDS Combo Cell provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into LVDS Combo Cell.

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LVDS guideLVDS tutorialCombo guideCombo tutorialCell guideCell tutorial

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