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DB-I2C-SMBus-MS-AMBA Controller IP Core.pdf

DB-I2C-MS-SMBUS-AMBA-DS-V1_1.pdf
Preview of DB-I2C-SMBus-MS-AMBA Controller IP Core
🔗 Source: digitalblocks.com
📊 Size: 232 KB
👤 Author: Digital Blocks, Inc.
⬇️ Downloads: 108

Summary

The Digital Blocks DB-I2C-SMBus-MS-AMBA-DS-V1.1 is an I2C/SMBus Master/Slave Controller IP Core that interfaces a microprocessor via AMBA AXI, AHB, or APB Bus to an I2C/SMBus Interconnect. Key features include:

- SMBus Compliance: SMBCLK timeout, SMBDAT hold time, and Address Resolution Protocol.
- Operating Modes: Master (Transmitter/Receiver) and Slave (Transmitter/Receiver).
- Bus Speeds: 10 KHz to 100 KHz for SMBus, and 100 Kb/s to 3.4 Mb/s for I2C.
- SMBus/I2C Compliance: Multi-Master, Clock Synchronization, Arbitration, and more.
- FIFO Memory & FSM Control: Offloads SMBus transfers from the processor.
- CPU Interface: Supports APB, AHB, AXI, AXI-lite, and Avalon SoC Interconnect fabrics.
- Interrupts: 13 internal interrupts with masking control.
- Compliance: AMBA, I2C, and SMBus specifications.
- Verification: Includes AMBA AXI, AHB, or APB Bus functional models for testing.
- Deliverables: RTL Verilog, technology-specific netlist, simulation test bench, datasheet, and user manual.
- Ordering: Contact Digital Blocks for technical, pricing, and support information.

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Description

The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller. It interfaces a microprocessor via AMBA AXI, AHB, or APB Bus to an I2C/SMBus Interconnect. Both I2C and SMBus protocols are supported.

Technical Information

  • File Format: PDF
  • File Size: 232 KB
  • Pages: 3
  • Language: EN
  • Author: Digital Blocks, Inc.
  • Total Downloads: 108
  • Last Updated: 6 days ago

Document Overview

This PDF document about DB-I2C-SMBus-MS-AMBA Controller IP Core provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into DB-I2C-SMBus-MS-AMBA Controller IP Core.

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