Designing 64-bit SRAM.pdf

- Topic: Static Random Access Memory (SRAM) Design and Power Consumption Analysis
- Author: Rupesh Maheshwari, Yogeshver Khandagre, and Alok Dube
- SRAM: Fast, low-power memory; building block of logic circuits; no refresh operation needed
- Design: 64-bit SRAM using 5T (5-transistor) and conventional 6T (6-transistor) cells; bottom-up approach using modular blocks
- Power Consumption:
- 5T SRAM: Reduces dynamic power consumption during write operations by preventing bit line discharge; 93% and 94% reduction in power dissipation for 0.12µm and 90nm technologies, respectively
- 6T SRAM: One bit line must be discharged regardless of written value, leading to higher power dissipation
- Operation Modes: Standby, Reading, Writing
- Standby: Word line not activated; access transistors disconnect storage cell from bit lines
- Reading: Precharge bit lines, activate word line, access transistors enable data transfer to bit lines
- Writing: Apply value to bit lines, activate word line, latch data in storage cell
- Simulation: 64-bit SRAM using 5T and 6T cells; comparison of power dissipation; analysis of read/write operations