I2C Master Controller.pdf

DB-I2C-M-Hs-Mode-DS-V1_1.pdf
Preview of I2C Master Controller
🔗 Source: digitalblocks.com
📊 Size: 247 KB
👤 Author: Digital Blocks, Inc.
⬇️ Downloads: 313

Summary

The Digital Blocks DB-I2C-M-Hs-Mode Controller IP Core is a master I2C controller that interfaces with a microprocessor via AMBA AXI/AHB/APB or Avalon bus to an I2C bus in Hs-Mode (3.4 Mbit/s), Fast-Mode Plus (1 Mbit/s), Fast-Mode (400 Kbit/s), or Standard-Mode (100 Kbit/s). It features a parameterized FIFO, finite state machine control, and supports multi-master, clock synchronization, arbitration, and repeated start. The core is fully synchronous, synthesizable, and compliant with AMBA and I2C specifications. It offers enhanced system-level features, including CPU interface, SCL/SDA spike filtering, and DMA transfer between I2C bus and memory. The DB-I2C-M-Hs-Mode is available in synthesizable RTL Verilog or technology-specific netlist, along with simulation test bench, datasheet, and user manual.

Description

The Digital Blocks DB-I2C-M-Hs-Mode Controller IP Core is a master I2C controller that interfaces with a microprocessor via AMBA AXI/AHB/APB or Avalon bus to...

Technical Information

  • File Format: PDF
  • File Size: 247 KB
  • Pages: 4
  • Language: EN
  • Author: Digital Blocks, Inc.
  • Total Downloads: 313
  • Last Updated: 2 weeks ago

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This PDF document about I2C Master Controller provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into I2C Master Controller.

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