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I3C Slave Controller.pdf

DB-I3C-S-SCL-CLK-REG-DS-V1_2.pdf
Preview of I3C Slave Controller
🔗 Source: digitalblocks.com
📊 Size: 263 KB
👤 Author: Digital Blocks, Inc.
⬇️ Downloads: 70

Summary

The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core for low power, low noise, and low VLSI footprint ASIC/ASSP/FPGA designs, processing I3C protocol and physical layers, and supporting I3C SDR up to 12.5 MHz bus speed and I2C bus speeds. It implements Slave-Transmit and Slave-Receive protocols according to MIPI I3C-Basic-Spec-ver1_0 and Philips I2C-Bus Specification, Version 2.1, with a fully-synchronous, synthesizable Verilog RTL core for easy integration into FPGA or ASIC design flows.

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Description

The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core for low power, low noise, and low VLSI footprint ASIC/ASSP/FPGA designs, processing I3C protocol...

Technical Information

  • File Format: PDF
  • File Size: 263 KB
  • Pages: 4
  • Language: EN
  • Author: Digital Blocks, Inc.
  • Total Downloads: 70
  • Last Updated: 6 days ago

Document Overview

This PDF document about I3C Slave Controller provides comprehensive information and guidance. Whether you're a beginner or advanced user, this resource offers valuable insights into I3C Slave Controller.

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